'''Publications''' 
 * [https://www.ssrg.ece.vt.edu/papers/tos19.pdf  M. M. Saad, R. Palmieri, B. Ravindran, "Lerna: Parallelizing Dependent Loops Using Speculation", ACM Transactions on Storage, To appear, 2019]
 * ('''''[attachment:systor-2018-best-paper-award.jpg:wiki:WikiStart?format=raw Best Paper!]''''') '''[https://www.ssrg.ece.vt.edu/papers/systor2018.pdf  M. Saad, R. Palmieri, B. Ravindran, "Lerna: Parallelizing Dependent Loops Using Speculation", The 11th ACM International Systems and Storage Conference (SYSTOR 2018), June 4-6, 2018, Haifa, Israel.]''' 
 * [http://www.ssrg.ece.vt.edu/papers/spaa16.pdf  M. Saad, R. Palmieri, A. Hassan, B. Ravindran, "Extending TM Primitives using Low Level Semantics", The 28th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2016), July 11 - 13, 2016, Asilomar State Beach, California, USA]
 * [http://www.ssrg.ece.vt.edu/papers/Transact16_paper_5.pdf  M. Saad, R. Palmieri, B. Ravindran, "Lerna: Transparent and Effective Speculative Loop Parallelization", ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2016), March 12, 2016, Barcelona, Spain]
 * [http://www.ssrg.ece.vt.edu/papers/ppopp_2016_saad.pdf  M. Saad, R. Palmieri, B. Ravindran, "On Ordering Transaction Commit", ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2016), Poster paper, March 12-16, 2016, Barcelona, Spain]
 * [/chrome/site/pub/PhdProposal_Saad.pdf  M. M. Saad, "Extracting Parallelism from Legacy Sequential Code Using Software Transactional Memory", PhD Dissertation Proposal, May 2015]
 * [/chrome/site/pub/hydra_hotpar.pdf  M. M. Saad, M. Mohamedin and B. Ravindran, "HydraVM: Extracting Parallelism from Legacy Sequential Code Using STM", In 4th USENIX Workshop on Hot Topics in Parallelism (HotPar '12), June 2012, Berkeley, CA]

'''Technical Reports'''
 * [/chrome/site/pub/hydra_tech.pdf  M. M. Saad, M. Mohamedin and B. Ravindran, "HydraVM: Technical Report", ECE Dept., Virginia Tech, Jan 2012]
 * [/chrome/site/pub/ByteSTM_tech.pdf  M. Mohamedin and B. Ravindran, "ByteSTM: Java Software Transactional Memory at the Virtual Machine Level, Technical Report", ECE Dept., Virginia Tech, Jan 2012]

'''Theses'''
 * [https://vtechworks.lib.vt.edu/handle/10919/71861 "Extracting Parallelism from Legacy Sequential Code Using Transactional Memory", Mohamed M. Saad, PhD Dissertation, July 2016]

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This work is supported in part by AFOSR under grant FA9550-14-1-0187. Any opinions, findings, and conclusions or recommendations expressed in this site are those of the author(s) and do not necessarily reflect the views of AFOSR.