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Publications
- M. Saad, R. Palmieri, A. Hassan, B. Ravindran, "Extending TM Primitives using Low Level Semantics", The 28th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2016), July 11 - 13, 2016, Asilomar State Beach, California, USA
- M. Saad, R. Palmieri, B. Ravindran, "Lerna: Transparent and Effective Speculative Loop Parallelization", ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2016), March 12, 2016, Barcelona, Spain
- M. Saad, R. Palmieri, B. Ravindran, "On Ordering Transaction Commit", ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2016), Poster paper, March 12-16, 2016, Barcelona, Spain
- M. M. Saad, "Extracting Parallelism from Legacy Sequential Code Using Software Transactional Memory", PhD Dissertation Proposal, May 2015
- M. M. Saad, M. Mohamedin and B. Ravindran, "HydraVM: Extracting Parallelism from Legacy Sequential Code Using STM", In 4th USENIX Workshop on Hot Topics in Parallelism (HotPar '12), June 2012, Berkeley, CA
Technical Reports
- M. M. Saad, M. Mohamedin and B. Ravindran, "HydraVM: Technical Report", ECE Dept., Virginia Tech, Jan 2012
- M. Mohamedin and B. Ravindran, "ByteSTM: Java Software Transactional Memory at the Virtual Machine Level, Technical Report", ECE Dept., Virginia Tech, Jan 2012
This work is supported in part by AFOSR under grant FA9550-14-1-0187. Any opinions, findings, and conclusions or recommendations expressed in this site are those of the author(s) and do not necessarily reflect the views of AFOSR.
